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| A W48C54A/55A Frequency Synthesizers Features * Proprietary crystal oscillator circuitry provides low REFOUT jitter, excellent duty cycle * Power-on delay feature ensures full VDD is reached prior to output activation * 3.3V and 5V operation supported including the VRE (Voltage Regulated Extended) specification for Pentium(R) processor * Pin and function compatible with AV9154/AV9155 * Integral PLL loop filter components ensures stable PLL operation in noisy system environment * Smooth frequency transition of CPU and 2XCPU outputs * Compatible with Intel X86 and other high-performance processors * Up to eight outputs for CPU and peripherals * Supports Green PC and notebook designs * Custom options available with metal layer change * High-performance, low-power CMOS * Available in 16- (150-mil) and 20-pin SOIC package (300-mil) Block Diagram VDD 14.318 MHz Xtal X1 Pin Configurations NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC 47.059MHz NC VDD GND REF(20MHz) NC OE XTAL X2 OSC 14.318 MHz X2 X1 VDD GND NC 32MHz GND PD PLL1 Fixed Outputs PLL2 2XCPU CPU FS0 X2 X1 VDD GND 40MHz 1 3 4 5 6 7 8 W48C54A-08 16 FS1 CPU NC VDD GND REF(20MHz) NC OE FS2:0 W48C54A-05, 09 2 15 14 13 12 11 10 9 GND OE 32MHz GND 1.843MHz X2 X1 VDD GND 24MHz 12MHz GND 1 3 4 5 6 7 8 16 FS1 FS0 CPU VDD GND 14.318MHz PD OE W48C54A-59 2 15 14 13 12 11 10 9 1.843MHz X2 X1 VDD GND 16MHz 24MHz 12MHz GND 0E 1 2 4 5 6 7 8 9 10 3 20 19 18 17 16 15 14 13 12 11 FS0 FS1 CPUCLK 2XCPUCLK VDD GND 14.318MHz 14.318MHz PD FS2 Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * W48C55A-61 CA 95134 * 408-943-2600 September 28 1999, rev. ** W48C54A/55A Pin Definitions Pin Name 1.843MHz 12MHz 16MHz REF 24MHz 32MHz 40MHz 47.059MHz 2XCPU CPU NC OE PD FS0 FS1 FS2 VDD GND X1 X2 I I I I I P G I O Pin Type O O O O O O O O O O Pin # -05, -09 N/A N/A N/A 11 N/A 7 6 N/A N/A 15 10, 14 9 N/A 1 16 N/A 4, 13 5, 8, 12 3 2 Pin # -08 N/A N/A N/A 11 N/A 7 N/A 15 N/A N/A 1, 6, 10, 14, 16 9 N/A N/A N/A N/A 4, 13 5, 8, 12 3 2 Pin # -59 1 7 N/A 11 6 N/A N/A N/A N/A 14 N/A 9 10 15 16 N/A 4, 13 5, 8, 12 3 2 Pin # -61 1 8 6 13, 14 7 N/A N/A N/A 17 18 N/A 10 12 20 19 11 4, 16 5, 9, 15 3 2 Pin Description Fixed 1.843-MHz output for serial I/O clock application Fixed 12-MHz output for keyboard clock application Fixed 16-MHz output for APIC or bus clock application Fixed Reference output. Fixed 24-MHz output for floppy drive or super I/O application Fixed 32-MHz output for ISA or PCI bus clock application Fixed 40-MHz output for SCSI clock application Fixed 47.059-MHz output 2X Clock Output (refer to Frequency Selection table) Clock Output (refer to Frequency Selection table) No Connect Output Enable, puts all outputs in high-impedance state when LOW Power Down input, puts device in power-down mode when LOW Frequency Selection input, LSB Frequency Selection input Frequency Selection input Power supply connection Ground connection Crystal connection or external clock frequency input Crystal connection, leave unconnected when driving X1 with external clock 2 W48C54A/55A Overview The W48C54A and W48C55A are general-purpose clock generator ICs. Some of the standard device options described in this document are designed for PC motherboard and embedded applications. Backward compatible with the W48C54 and W48C55, these dual-PLL clock devices incorporate an improved crystal oscillator as well as other refinements. On-chip loop filter components ensure stable operation even with the noise typical of a digital system. Device functionality, including input/output options and frequency selection is determined by a single metal mask that allows quick-turn customization capability. Both 3.3- and 5-volt operation are supported. The improved crystal oscillator of the W48C54A and W48C55A most notably provides improved duty cycle at the reference output(s). With this new design, duty cycle is not affected by varying operating conditions such as with the addition of external crystal load capacitors. Clock jitter from the 14.318-MHz output(s) is also improved, as is the crystal oscillation frequency accuracy. Like the W48C54 and W48C55, the W48C54A and W48C55A have a unique power-on delay circuit. This feature allows compatibility with certain microprocessor devices that cannot withstand clock input toggling until full supply voltage is reached. Upon application of power to the V DD pins, the W48C54A/55A output clocks are delayed (held LOW) for approximately 15 ms, after which they assume normal operation. can best be used by power management systems where it is frequently necessary to slow down the clock to conserve power. By controlling the rate of frequency transition, both devices are designed to be compatible with Intel(R) cycle-to-cycle processor timing specifications. Power down capability is available in selected versions of the W48C54A and W48C55A. When PD is active (LOW), the device is placed in a standby mode during which power dissipation is at its minimum; all clock outputs are forced LOW. Partial power is also an available option, wherein selected outputs are disabled or enabled according to a logic input. Table 1. Frequency Selection for W48C54A -05 FS1 0 0 1 1 FS0 0 1 0 1 47.000 47.000 27.000 36.000 20 -09 54.000 18.800 27.000 36.000 20 -59 50.113 40.568 66.817 33.409 14.318 CPU (MHz) CPU (MHz) CPU (MHz) Input/REF Table 2. Frequency Selection for W48C55A -61 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 2XCPU (MHz) 8 16 32 40 50 66.66 80 100[1] CPU (MHz) 4 8 16 20 25 33.33 40 50[1] Functional Description The Functional Block Diagram shows the reference clock source can be a crystal connected across the X1 and X2 input pins, alternatively input clock connected to the X1 input pin. In the latter case, the X2 pin is left open. With either source as reference, both the W48C54A and W48C55A generate all necessary clocks at their respective frequencies to drive the specified clocks. To provide the broadest possible range of frequencies typically required for CPU mother-board designs, the target frequencies can be selected via up to four select inputs. Consult the appropriate tables for the clock selection range. In addition, the W48C54A/55A can provide rebuffered reference clock outputs. Both the W48C54A and W48C55A offer smooth transitions when changing CPU/2XCPU output frequency. This feature Note: 1. Not guaranteed when VDD < 4.5V. 3 W48C54A/55A Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD TSTG TA VIN PD Description VDD referenced to GND Storage Temperature Operating Temperature V on I/O ref to GND Power Dissipation above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating 7.0 -40 to +150 0 to +70 GND-5.0 to VDD+5.0 0.5 Unit V C C V W Electrical Characteristics ) 5.0V DC Characteristics (0C < TA < 70C, VDD = 5.0V10%) Parameter VIL VIH IIL IIH VOL VOH VOH IDD FD ISC IDDSTBY CIN CL RP Description Input Low Voltage Input High Voltage Input Low Current[2] Input High Current Output Low Voltage Output High Voltage Output High Voltage Supply Current [3] [4] Test Condition VDD = 5.0V VDD = 5.0V VIN = 0V VIN = VDD IOL = 4 mA IOH = -1 mA, V DD=5V IOH = -4 mA, V DD=5V No load Over supply and temperature Each output clock Min 2.0 Typ Max 0.8 -100 10 0.4 Unit V V A A V V V VDD-0.4 VDD-0.8 25 0.002 25 40 300 40 0.01 mA % mA A Output Frequency Change Short Circuit Current Supply Current, Power Down[5] Input Capacitance Load Capacitance Pull-up Resistor Value Except pins X1, X2 Pins X1 and X2 Except X1, X2 20 250 10 pF pF k Notes: 2. Includes pull-up resistor. 3. No output load capacitance, CPU or 2XCPU running at 50 MHz. Power supply current can change with different mask configuration. 4. Consideration of reference crystal shift only. 5. With full chip power-down pin LOW. 4 W48C54A/55A 5.0V AC Characteristics (0C < TA < 70C, VDD = 5.0V 10%) Parameter TICR TICF TR TR TF TF DT TJAB FI TSK TFT Description Input Clock Rise Time Input Clock Fall Time Output Rise Time, 0.8 to 2.0V Rise Time, 20% to 80% VDD Output Fall Time, 2.0 to 0.8V Fall Time, 80% to 20% VDD Duty Cycle, All Outputs Jitter, Absolute Input Frequency Clock Skew between CPU and 2XCPU outputs Frequency Transition Time From 8-100 MHz 40 25-pF load 25-pF load 25-pF load 25-pF load 25-pF load 16-100 MHz clocks 14.318 1.0 50 40/60 1 2 1 2 50/50 Conditions Min Typ Max 20 20 2 4 2 4 60/40 700 Unit ns ns ns ns ns ns % ps MHz ns ms 3.3V DC Characteristics (0C < TA < 70C, VDD = 3.3V10%) Parameter VIL VIH IIL IIH VOL VOH IDD FD ISC CIN CL RP Description Input Low Voltage Input High Voltage Input Low Current [2] Test Condition VDD = 3.3V VDD = 3.3V VIN = 0V VIN = V DD IOL = 4 mA IOH = -4 mA, VDD=3.3V No load [4] Min 0.7*VDD Typ Max 0.15*VDD -100 10 0.4 Unit V V A A V V mA % mA pF pF k Input High Current Output Low Voltage Output High Voltage Supply Current [3] 2.4 20 0.002 25 40 10 20 250 35 0.01 Output Frequency Change Short Circuit Current Input Capacitance Load Capacitance Pull-up Resistor Value Over supply and temperature Each output clock Except pins X1, X2 Pins X1 and X2 Except X1, X2 3.3V AC Characteristics (0C < TA < 70C, VDD = 3.3V 10%) Parameter TICR TICF TR TF DT TJAB FI TSK TFT Description Input Clock Rise Time Input Clock Fall Time Rise Time, 20% to 80% VDD Fall Time, 80% to 20% VDD Duty Cycle, All Outputs Jitter, Absolute Input Frequency Clock Skew between CPU and 2XCPU outputs Frequency Transition Time From 8-100 MHz 40 15-pF load 15-pF load 15-pF load 16-80 MHz clocks 14.318 1.0 50 40/60 2 2 50/50 Conditions Min Typ Max 20 20 4 4 60/40 700 Unit ns ns ns ns % ps MHz ns ms 5 W48C54A/55A Recommended Board Layout: W48C54A/55A For optimum performance in system applications, the power supply decoupling scheme shown in Figure 1 should be used. All GND pins are connected to the ground plane. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitors should be placed as close to the VDD pins as possible, otherwise the increased trace inductance will negate its decoupling capability. the 10-F decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. VDD Optional Ferrite Bead 10 F VDD 0.1 F GND GND VDD GND 0.1 F Figure 1. Recommended Circuit Configuration Ordering Information Ordering Code W48C54A W48C55A Document #: 38-00803 Freq. Mask Code 05, 08, 09, 59 61 Package Name G G Package Type 16-pin Plastic SOIC (150-mil) 20-pin Plastic SOIC (300-mil) 6 W48C54A/55A Package Diagrams 20-Pin Small Outline Integrated Circuit (SOIC, 300-mil) 7 W48C54A/55A Package Diagrams (continued) 16-Pin Small Outline Integrated Circuit (SOIC, 150-mil) (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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